A Fully Differential Read-decoupled 7-t Sram Cell to Reduce Dynamic Power Consumption

To improve the performance of an SRAM cell and reduce the area consumption, researchers are scaling down the technology node of MOSFET. But power consumption is not yet improved below 65-nm technology node. Since then the VDD (supply voltage) remains more or less constant and dynamic power consumption improvement is almost stagnated, while leakage current increases exponentially. Hence, prime area of concern of present days circuit is to reduce the power consumption with minimum device size. In this article a fully differential read decoupled 7T SRAM cell is proposed that consumes substantial amount of less read and write power. Side by side it shows 4% (10.57×) shorter read (write) delay and 4×/9.24% improvement in RSNM/WSNM (Read static noise margin/write static noise margin) @ 700 mV.